@inproceedings{cd39a133a54b4082acf0c891fce2c1ba,
title = "Design of a 26GHz phase-locked frequency synthesizer in 0.13um CMOS",
abstract = "A 26GHz Phase-Locked Frequency Synthesizer in 0.13um CMOS process is designed. This frequency synthesizer generates quadrature outputs at 26GHz. The PLL utilizing a QVCO with tuning range from 23.75GHz to 28.25GHz can be locked from 24GHz to 28GHz. The power consumption of the circuit is 34mW with a power supply of 1.2V. The phase noise of the QVCO is -95dBc/Hz at 1MHz offset and the Q-mismatch is 1.7°. Circuits are simulated by Cadence Spectre in 0.13μm Standard CMOS Process.",
keywords = "CMOS, Frequency synthesizer, High-speed, Phase-locked loop",
author = "Yueyang Chen and Shun'an Zhong and Hua Dang",
year = "2009",
doi = "10.1109/CMC.2009.213",
language = "English",
isbn = "9780769535012",
series = "Proceedings - 2009 WRI International Conference on Communications and Mobile Computing, CMC 2009",
pages = "541--544",
booktitle = "Proceedings - 2009 WRI International Conference on Communications and Mobile Computing, CMC 2009",
note = "2009 WRI International Conference on Communications and Mobile Computing, CMC 2009 ; Conference date: 06-01-2009 Through 08-01-2009",
}