Design and efficient implementation of airborne shock signal process chip based on FPGA

Design, implementation and application of a three-channel airborne shock signal process chip based on FPGA is described. Pipeline processing can ensure the time of computing the peak acceleration for a single-degree-of freedom system. It provides good conditions for optimizing the design parameters of the whole device because the power consumption of the device and processing accuracy of MaxiMax Shock Spectrum mainly depend on the sampling frequency, at the same time both are conflicting. After lots of tests, airborne processors with the chip have been applied to several experiments. As a result, bandwidth of shock signals is greatly compressed by processing shock signal on board. In addition signal peak detection error is reduced and measurement dynamic range is extended. Moreover, verification of the data becomes much easier on the ground.