ASIC design of high-speed low-power HDLC controller

He Chen; Yue Qiu Han

ASIC design of high-speed low-power HDLC controller

He Chen^*, Yue Qiu Han

^*此作品的通讯作者

信息与电子学院

Beijing Institute of Technology

科研成果: 期刊稿件 › 文章 › 同行评审

2 引用（Scopus）

摘要

Combined with the engineering requirement, a high-speed low-power ASIC (application specific integrated circuit) design of HDLC (high speed data link control) controller based on RS-485 bus is given. Based on the principle of top-Down design, this ASIC design uses multi-techniques to reduce its die area and dynamic power, and overcomes some problems appeared frequently in application of the RS-485 circuits formed by the standard interface chips. This design also improves the system reliability and reduces the system area.

源语言	英语
页（从-至）	66-69
页数	4
期刊	Journal of Beijing Institute of Technology (English Edition)
卷	12
期	SUPPL.
出版状态	已出版 - 12月 2003

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Chen, H., & Han, Y. Q. (2003). ASIC design of high-speed low-power HDLC controller. Journal of Beijing Institute of Technology (English Edition), 12(SUPPL.), 66-69.

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ASIC design of high-speed low-power HDLC controller

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