摘要
A concurrent error detection design was proposed for discrete cosine transform, and based on it an improved design was presented. DCT is realized by butterfly architecture of B.G.Lee fast algorithm, and algorithm-based fault tolerance is used for CED. The proposed design allows 100% throughput and high fault coverage with a very low increment of hardware coverage. The fault coverage of this scheme was analyzed and the conclusion was given.
| 源语言 | 英语 |
|---|---|
| 页（从-至） | 30-33 |
| 页数 | 4 |
| 期刊 | Tien Tzu Hsueh Pao/Acta Electronica Sinica |
| 卷 | 27 |
| 期 | 8 |
| 出版状态 | 已出版 - 8月 1999 |
指纹
探究 'Algorithm-based concurrent error detection scheme for DCT networks' 的科研主题。它们共同构成独一无二的指纹。引用此
Chen, H., Mao, Z., & Ye, Y. (1999). Algorithm-based concurrent error detection scheme for DCT networks. Tien Tzu Hsueh Pao/Acta Electronica Sinica, 27(8), 30-33.