A single channel 8 bit 1.4 GS/s folding and interpolation ADC

Youtao Zhang; Xiaopeng Li; Min Zhang; Ao Liu; Feng Qian; Chen Chen

A single channel 8 bit 1.4 GS/s folding and interpolation ADC

Youtao Zhang^*, Xiaopeng Li, Min Zhang, Ao Liu, Feng Qian, Chen Chen

^*此作品的通讯作者

Nanjing Electronic Devices Institute

科研成果: 期刊稿件 › 文章 › 同行评审

摘要

A 1.4 GS/s 8 bit ADC is demonstrated in 0.18 μm CMOS. The chip realizes cascade folding and interpolation with resistive averaging and digital calibration. Test results show that the ENOB could be 6.4 bit with 480 mW power dissipation while operating at 1.4 GS/s. The proposed effective calibration methods could improve the static and dynamic performance of ADC.

源语言	英语
页（从-至）	393-397
页数	5
期刊	Guti Dianzixue Yanjiu Yu Jinzhan/Research and Progress of Solid State Electronics
卷	31
期	4
出版状态	已出版 - 8月 2011
已对外发布	是

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Zhang, Y., Li, X., Zhang, M., Liu, A., Qian, F., & Chen, C. (2011). A single channel 8 bit 1.4 GS/s folding and interpolation ADC. Guti Dianzixue Yanjiu Yu Jinzhan/Research and Progress of Solid State Electronics, 31(4), 393-397.

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abstract = "A 1.4 GS/s 8 bit ADC is demonstrated in 0.18 μm CMOS. The chip realizes cascade folding and interpolation with resistive averaging and digital calibration. Test results show that the ENOB could be 6.4 bit with 480 mW power dissipation while operating at 1.4 GS/s. The proposed effective calibration methods could improve the static and dynamic performance of ADC.",

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AU - Liu, Ao

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AU - Chen, Chen

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KW - Analog-to-digital conversion

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A single channel 8 bit 1.4 GS/s folding and interpolation ADC

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