摘要
In this paper, a light-weighted pipelined serial Viterbi Decoder is implemented for resource saving purpose. The trace back module of the decoder consumes fewer logical resources by employing a RAM-based Register Exchange architecture. All the metric and trace back bits are stored in the RAM to save logical resources. Synthesis results show that, the proposed architecture can save more than half of resource utilization than fabric IP core and has the minimum logic consumption than almost other schemes we can find with nearly no performance loss.
| 源语言 | 英语 |
|---|---|
| 主期刊名 | Proceedings - 2011 International Conference on Instrumentation, Measurement, Computer, Communication and Control, IMCCC 2011 |
| 页 | 601-604 |
| 页数 | 4 |
| DOI | |
| 出版状态 | 已出版 - 2011 |
| 活动 | 1st International Conference on Instrumentation and Measurement, Computer, Communication and Control, IMCCC2011 - Beijing, 中国 期限: 21 10月 2011 → 23 10月 2011 |
出版系列
| 姓名 | Proceedings - 2011 International Conference on Instrumentation, Measurement, Computer, Communication and Control, IMCCC 2011 |
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会议
| 会议 | 1st International Conference on Instrumentation and Measurement, Computer, Communication and Control, IMCCC2011 |
|---|---|
| 国家/地区 | 中国 |
| 市 | Beijing |
| 时期 | 21/10/11 → 23/10/11 |
指纹
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Wu, Z., Hou, S., & Li, H. (2011). A light-weighted viterbi decoder implemented by FPGA. 在 Proceedings - 2011 International Conference on Instrumentation, Measurement, Computer, Communication and Control, IMCCC 2011 (页码 601-604). 文章 6154180 (Proceedings - 2011 International Conference on Instrumentation, Measurement, Computer, Communication and Control, IMCCC 2011). https://doi.org/10.1109/IMCCC.2011.155