A fully integrated 60-GHz 5-Gb/s QPSK transceiver with T/R switch in 65-nm CMOS

A fully integrated 60-GHz 5-Gb/s quadrature phase-shift keying (QPSK) transceiver with the transmit/receive (T/R) switch in 65-nm CMOS is presented. By utilizing the co-design of the T/R switch with the power amplifier (PA)/low-noise amplifier, \pi-type wideband passive network technique, as well as the modified distributed-amplifier-based PA, the RF bandwidth of the transmitter (TX)/receiver (RX) is extended to 5 GHz. An inductorless wideband programmable gain amplifier with negative capacitive neutralization, consisting of two modified Cherry-Hooper amplifier stages, provides 18-dB variable gain range with enough bandwidth. Due to the proposed bandwidth extension techniques, the measured double-side link bandwidth of the TX/RX is wider than 5 GHz so that 5-Gb/s QPSK communication could be supported. A direct QPSK modulator and mixed-signal QPSK demodulator are integrated to avoid the high-power high-complexity analog-digital converter/digital-analog converter and high-speed digital baseband processing. Together with the integrated T/R switch, the power consumption and the cost of the transceiver are significantly lowered while achieving up to 5-Gb/s data rate. The local oscillating signals and various clocks are provided by a fully differential phase-locked loop frequency synthesizer with -97.2-dBc/Hz phase noise at 1-MHz offset from a 40-GHz carrier. The measured error vector magnitude of the TX is -21.9 dB, while the bit error rate of the RX with a -52-dBm sine-wave input is below 8e-7 when transmitting/receiving 5-Gb/s data. The transceiver is powered by 1.0- and 1.2-V supply (except the phase-frequency detector and charge-pump in the frequency synthesizer, which are powered by a 2.5-V supply) and consumes 135 mW in the TX mode and 176 mW in the RX mode, with a chip area of 3 mm \times 2 mm.