Abstract
Ultra-deep through-silicon-vias (TSVs) are of great demand for 3D heterogeneous integration. However, most reported deep TSVs adopt double-sided silicon etching and electroplating, which dramatically increases the complexity and cost of the fabrication process. This letter focuses on how to achieve a high-quality Cu seed layer in ultra-deep vias, which is the key technology for the fabrication of single-sided ultra-deep TSVs. By proposing a novel pulsed ultrasound-Assisted electroless plating method, continuous and dense Cu seed layers are successfully deposited in silicon vias with a depth as large as 580 ~\mu \text{m}. Combined with a conformal Cu electroplating and a vacuum-Assisted Benzocyclobutene (BCB) refilling, BCB-core annular Cu TSVs with depths up to 580 ~\mu \text{m} and aspect ratios up to 8 are successfully fabricated. Measured results show that the fabricated TSVs exhibit a depletion capacitance of 1.75 pF, a low leakage current of 0.44 pA at 20 V, indicating good electrical properties.
Original language | English |
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Pages (from-to) | 426-429 |
Number of pages | 4 |
Journal | IEEE Electron Device Letters |
Volume | 43 |
Issue number | 3 |
DOIs | |
Publication status | Published - 1 Mar 2022 |
Keywords
- 3D heterogeneous integration
- Ultra-deep annular TSV
- electroless plating
- pulsed ultrasound
- seed layer