Abstract
To address performance and accuracy problems caused by synchronization as simulating a many-core computer in parallel, two-level synchronous mechanism is proposed. The first level synchronization functioning among all nodes ensures the global time order. The second level synchronization maintains the time order between high level caches and the NoC (Network on Chip) router on one node, which improves parallelism without hurting fidelity of models. The theoretical analysis reveals the upper and lower bounds on the performance of proposed mechanism. And the experiment shows it obtains good speed-up and reasonable scalability.
| Original language | English |
|---|---|
| Pages (from-to) | 2806-2813 |
| Number of pages | 8 |
| Journal | Xitong Fangzhen Xuebao / Journal of System Simulation |
| Volume | 25 |
| Issue number | 12 |
| Publication status | Published - Dec 2013 |
| Externally published | Yes |
Keywords
- Lookahead
- Many core architecture
- Parallel simulation
- Synchronous mechanism