TY - JOUR
T1 - Supporting differentiated services in computers via programmable architecture for resourcing-on-demand (PARD)
AU - Ma, Jiuyue
AU - Sui, Xiufeng
AU - Sun, Ninghui
AU - Li, Yupeng
AU - Yu, Zihao
AU - Huang, Bowen
AU - Xu, Tianni
AU - Yao, Zhicheng
AU - Chen, Yun
AU - Wang, Haibin
AU - Zhang, Lixin
AU - Bao, Yungang
N1 - Publisher Copyright:
Copyright © 2015 ACM.
PY - 2015/4
Y1 - 2015/4
N2 - This paper presents PARD, a programmable architecture for resourcing-on-demand that provides a new programming interface to convey an application's high-level information like quality-of-service requirements to the hardware. PARD enables new functionalities like fully hardware-supported virtualization and differentiated services in computers. PARD is inspired by the observation that a computer is inherently a network in which hardware components communicate via packets (e.g., over the NoC or PCIe). We apply principles of software-defined networking to this intra-computer network and address three major challenges. First, to deal with the semantic gap between high-level applications and underlying hardware packets, PARD attaches a high-level semantic tag (e.g., a virtual machine or thread ID) to each memory-access, I/O, or interrupt packet. Second, to make hardware components more manageable, PARD implements programmable control planes that can be integrated into various shared resources (e.g., cache, DRAM, and I/O devices) and can differentially process packets according to tag-based rules. Third, to facilitate programming, PARD abstracts all control planes as a device file tree to provide a uniform programming interface via which users create and apply tag-based rules. Full-system simulation results show that by co-locating latency critical memcached applications with other workloads PARD can improve a four-core computer's CPU utilization by up to a factor of four without significantly increasing tail latency. FPGA emulation based on a preliminary RTL implementation demonstrates that the cache control plane introduces no extra latency and that the memory control plane can reduce queueing delay for high-priority memory-access requests by up to a factor of 5.6.
AB - This paper presents PARD, a programmable architecture for resourcing-on-demand that provides a new programming interface to convey an application's high-level information like quality-of-service requirements to the hardware. PARD enables new functionalities like fully hardware-supported virtualization and differentiated services in computers. PARD is inspired by the observation that a computer is inherently a network in which hardware components communicate via packets (e.g., over the NoC or PCIe). We apply principles of software-defined networking to this intra-computer network and address three major challenges. First, to deal with the semantic gap between high-level applications and underlying hardware packets, PARD attaches a high-level semantic tag (e.g., a virtual machine or thread ID) to each memory-access, I/O, or interrupt packet. Second, to make hardware components more manageable, PARD implements programmable control planes that can be integrated into various shared resources (e.g., cache, DRAM, and I/O devices) and can differentially process packets according to tag-based rules. Third, to facilitate programming, PARD abstracts all control planes as a device file tree to provide a uniform programming interface via which users create and apply tag-based rules. Full-system simulation results show that by co-locating latency critical memcached applications with other workloads PARD can improve a four-core computer's CPU utilization by up to a factor of four without significantly increasing tail latency. FPGA emulation based on a preliminary RTL implementation demonstrates that the cache control plane introduces no extra latency and that the memory control plane can reduce queueing delay for high-priority memory-access requests by up to a factor of 5.6.
KW - Data Center
KW - Hardware/Software Interface
KW - QoS
UR - http://www.scopus.com/inward/record.url?scp=84950992255&partnerID=8YFLogxK
U2 - 10.1145/2694344.2694382
DO - 10.1145/2694344.2694382
M3 - Article
AN - SCOPUS:84950992255
SN - 1523-2867
VL - 50
SP - 131
EP - 143
JO - ACM SIGPLAN Notices
JF - ACM SIGPLAN Notices
IS - 4
ER -