Abstract
A novel digital pulse compression algorithm based on field programmable gate array (FPGA) is proposed, and two radix-4 butterflies are used in the algorithm. Parallel memory accessing for the decimation-in-time radix-4 FFT algorithm is discussed based on the "in-place" principle. And two radix-4 butterflies are calculated at the same time. Two digital pulse compression (DPC) modules are used to accomplish DPC of the odd number and the even number at the same time. Results show that a complex 4 K point pulse compression is calculated about 67 μs at 100 MHz. Experiments show that the algorithm is feasible.
| Original language | English |
|---|---|
| Pages (from-to) | 11-14 |
| Number of pages | 4 |
| Journal | Shuju Caiji Yu Chuli/Journal of Data Acquisition and Processing |
| Volume | 21 |
| Issue number | SUPPL. |
| Publication status | Published - Dec 2006 |
Keywords
- Biphase coded signals
- Field programmable gate array (FPGA)
- Pulse compression
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Wang, C., Tian, L., & Gao, M. (2006). Pulse compression based on FPGA using two butterflies. Shuju Caiji Yu Chuli/Journal of Data Acquisition and Processing, 21(SUPPL.), 11-14.