Abstract
A new method of built-in self-testing for pulse doppler radar digital signal processor was advanced. The method is between board-level testing and system-level testing, integrating system adjustment, on-line testing and off-line testing in one BIT system. The implementation of BIT was offered, and the fault-coverage-rate of "data rearrangement" module was calculated. This method had been successfully applied to a PD radar.
| Original language | English |
|---|---|
| Pages (from-to) | 748-752 |
| Number of pages | 5 |
| Journal | Beijing Ligong Daxue Xuebao/Transaction of Beijing Institute of Technology |
| Volume | 17 |
| Issue number | 6 |
| Publication status | Published - 1997 |
Keywords
- Built-in self-test
- Digital signal processor
- Pulse doppler radar
- Testable design