Low-Temperature Fabrication of Solution-Processed InGaZnO Thin-Film Transistors

Yonghua Chen; Zhinong Yu; Xuyang Li; Jin Cheng

doi:10.1109/CAD-TFT.2018.8608055

Low-Temperature Fabrication of Solution-Processed InGaZnO Thin-Film Transistors

Yonghua Chen, Zhinong Yu, Xuyang Li, Jin Cheng

School of Optics and Photonics

Beijing Institute of Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

We report a novel method for fabricating solution-processed quaternary In-Ga-Zn-O (IGZO) thin-film transistors (TFTs) at low annealing temperature. The method is to spin coat such binary oxide layers as Ga ₂ O ₃ , ZnO and In ₂ O ₃ consecutively and then anneal the layers at 250 °C. Finally, due to vertical diffusion of the binary oxides, the IGZO film with a vertically gradient In, Ga, Zn distribution (defined as vd-IGZO) is obtained and used as the channel layer of TFT. Compared with conventional IGZO (con-IGZO) TFTs annealing at 380°C, the vd-IGZO TFTs have better electrical performances.

Original language	English
Title of host publication	2018 9th International Conference on Computer Aided Design for Thin-Film Transistor Technologies, CAD-TFT 2018
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781728100968
DOIs	https://doi.org/10.1109/CAD-TFT.2018.8608055
Publication status	Published - 10 Jan 2019
Event	9th International Conference on Computer Aided Design for Thin-Film Transistor Technologies, CAD-TFT 2018 - Shenzhen, China Duration: 16 Nov 2018 → 18 Nov 2018

Publication series

Name	2018 9th International Conference on Computer Aided Design for Thin-Film Transistor Technologies, CAD-TFT 2018

Conference

Conference	9th International Conference on Computer Aided Design for Thin-Film Transistor Technologies, CAD-TFT 2018
Country/Territory	China
City	Shenzhen
Period	16/11/18 → 18/11/18

Keywords

low-temperature preparation
thin-film transistors

Access to Document

10.1109/CAD-TFT.2018.8608055

Cite this

Chen, Y., Yu, Z., Li, X., & Cheng, J. (2019). Low-Temperature Fabrication of Solution-Processed InGaZnO Thin-Film Transistors. In 2018 9th International Conference on Computer Aided Design for Thin-Film Transistor Technologies, CAD-TFT 2018 Article 8608055 (2018 9th International Conference on Computer Aided Design for Thin-Film Transistor Technologies, CAD-TFT 2018). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CAD-TFT.2018.8608055

Chen, Yonghua ; Yu, Zhinong ; Li, Xuyang et al. / Low-Temperature Fabrication of Solution-Processed InGaZnO Thin-Film Transistors. 2018 9th International Conference on Computer Aided Design for Thin-Film Transistor Technologies, CAD-TFT 2018. Institute of Electrical and Electronics Engineers Inc., 2019. (2018 9th International Conference on Computer Aided Design for Thin-Film Transistor Technologies, CAD-TFT 2018).

@inproceedings{d311b8309cbf42f5924a68f670fc59c8,

title = "Low-Temperature Fabrication of Solution-Processed InGaZnO Thin-Film Transistors",

abstract = " We report a novel method for fabricating solution-processed quaternary In-Ga-Zn-O (IGZO) thin-film transistors (TFTs) at low annealing temperature. The method is to spin coat such binary oxide layers as Ga 2 O 3 , ZnO and In 2 O 3 consecutively and then anneal the layers at 250 °C. Finally, due to vertical diffusion of the binary oxides, the IGZO film with a vertically gradient In, Ga, Zn distribution (defined as vd-IGZO) is obtained and used as the channel layer of TFT. Compared with conventional IGZO (con-IGZO) TFTs annealing at 380°C, the vd-IGZO TFTs have better electrical performances.",

keywords = "low-temperature preparation, thin-film transistors",

author = "Yonghua Chen and Zhinong Yu and Xuyang Li and Jin Cheng",

note = "Publisher Copyright: {\textcopyright} 2018 IEEE.; 9th International Conference on Computer Aided Design for Thin-Film Transistor Technologies, CAD-TFT 2018 ; Conference date: 16-11-2018 Through 18-11-2018",

year = "2019",

month = jan,

day = "10",

doi = "10.1109/CAD-TFT.2018.8608055",

language = "English",

series = "2018 9th International Conference on Computer Aided Design for Thin-Film Transistor Technologies, CAD-TFT 2018",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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address = "United States",

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Chen, Y, Yu, Z, Li, X & Cheng, J 2019, Low-Temperature Fabrication of Solution-Processed InGaZnO Thin-Film Transistors. in 2018 9th International Conference on Computer Aided Design for Thin-Film Transistor Technologies, CAD-TFT 2018., 8608055, 2018 9th International Conference on Computer Aided Design for Thin-Film Transistor Technologies, CAD-TFT 2018, Institute of Electrical and Electronics Engineers Inc., 9th International Conference on Computer Aided Design for Thin-Film Transistor Technologies, CAD-TFT 2018, Shenzhen, China, 16/11/18. https://doi.org/10.1109/CAD-TFT.2018.8608055

Low-Temperature Fabrication of Solution-Processed InGaZnO Thin-Film Transistors. / Chen, Yonghua; Yu, Zhinong; Li, Xuyang et al.
2018 9th International Conference on Computer Aided Design for Thin-Film Transistor Technologies, CAD-TFT 2018. Institute of Electrical and Electronics Engineers Inc., 2019. 8608055 (2018 9th International Conference on Computer Aided Design for Thin-Film Transistor Technologies, CAD-TFT 2018).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Low-Temperature Fabrication of Solution-Processed InGaZnO Thin-Film Transistors

AU - Chen, Yonghua

AU - Yu, Zhinong

AU - Li, Xuyang

AU - Cheng, Jin

PY - 2019/1/10

Y1 - 2019/1/10

N2 - We report a novel method for fabricating solution-processed quaternary In-Ga-Zn-O (IGZO) thin-film transistors (TFTs) at low annealing temperature. The method is to spin coat such binary oxide layers as Ga 2 O 3 , ZnO and In 2 O 3 consecutively and then anneal the layers at 250 °C. Finally, due to vertical diffusion of the binary oxides, the IGZO film with a vertically gradient In, Ga, Zn distribution (defined as vd-IGZO) is obtained and used as the channel layer of TFT. Compared with conventional IGZO (con-IGZO) TFTs annealing at 380°C, the vd-IGZO TFTs have better electrical performances.

AB - We report a novel method for fabricating solution-processed quaternary In-Ga-Zn-O (IGZO) thin-film transistors (TFTs) at low annealing temperature. The method is to spin coat such binary oxide layers as Ga 2 O 3 , ZnO and In 2 O 3 consecutively and then anneal the layers at 250 °C. Finally, due to vertical diffusion of the binary oxides, the IGZO film with a vertically gradient In, Ga, Zn distribution (defined as vd-IGZO) is obtained and used as the channel layer of TFT. Compared with conventional IGZO (con-IGZO) TFTs annealing at 380°C, the vd-IGZO TFTs have better electrical performances.

KW - low-temperature preparation

KW - thin-film transistors

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DO - 10.1109/CAD-TFT.2018.8608055

M3 - Conference contribution

AN - SCOPUS:85061920143

T3 - 2018 9th International Conference on Computer Aided Design for Thin-Film Transistor Technologies, CAD-TFT 2018

BT - 2018 9th International Conference on Computer Aided Design for Thin-Film Transistor Technologies, CAD-TFT 2018

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 9th International Conference on Computer Aided Design for Thin-Film Transistor Technologies, CAD-TFT 2018

Y2 - 16 November 2018 through 18 November 2018

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Chen Y, Yu Z, Li X, Cheng J. Low-Temperature Fabrication of Solution-Processed InGaZnO Thin-Film Transistors. In 2018 9th International Conference on Computer Aided Design for Thin-Film Transistor Technologies, CAD-TFT 2018. Institute of Electrical and Electronics Engineers Inc. 2019. 8608055. (2018 9th International Conference on Computer Aided Design for Thin-Film Transistor Technologies, CAD-TFT 2018). doi: 10.1109/CAD-TFT.2018.8608055

Low-Temperature Fabrication of Solution-Processed InGaZnO Thin-Film Transistors

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