FPGA-Based Implementation of Reconfigurable Floating-Point FIR Digital Filter

Ning Zhang; Xin Wei; Bingyi Li; He Chen

doi:10.1007/978-981-13-9409-6_47

FPGA-Based Implementation of Reconfigurable Floating-Point FIR Digital Filter

Ning Zhang, Xin Wei, Bingyi Li, He Chen^*

^*Corresponding author for this work

School of Optics and Photonics

Beijing Institute of Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Citation (Scopus)

Abstract

As a critical digital signal processing method, finite impulse response (FIR) digital filter is widely used in radar signal processing, synthetic aperture radar (SAR) signal processing, etc. Furthermore, an efficient FIR hardware implementation contributes to the practical application of these processing. However, as a computation-intensive operation, the multiple high order FIR digital filter consumes a lot of hardware resources when implemented in commonly used chips such as field-programmable gate array (FPGA). In this paper, a reconfigurable FIR digital filter architecture is presented, which can perform different order FIR filtering operation without FPGA re-programming. In the experiment, the proposed FIR digital filter architecture was implemented and validated on the Xilinx Zedboard Evaluation Kit. The experimental results demonstrate that this design has a low consumption of hardware resources and can achieve real-time processing performance for digital signal processing in the practical applications.

Original language	English
Title of host publication	Communications, Signal Processing, and Systems - Proceedings of the 8th International Conference on Communications, Signal Processing, and Systems, CSPS 2019
Editors	Qilian Liang, Wei Wang, Xin Liu, Zhenyu Na, Min Jia, Baoju Zhang
Publisher	Springer
Pages	400-407
Number of pages	8
ISBN (Print)	9789811394089
DOIs	https://doi.org/10.1007/978-981-13-9409-6_47
Publication status	Published - 2020
Event	8th International Conference on Communications, Signal Processing, and Systems, CSPS 2019 - Urumqi, China Duration: 20 Jul 2019 → 22 Jul 2019

Publication series

Name	Lecture Notes in Electrical Engineering
Volume	571 LNEE
ISSN (Print)	1876-1100
ISSN (Electronic)	1876-1119

Conference

Conference	8th International Conference on Communications, Signal Processing, and Systems, CSPS 2019
Country/Territory	China
City	Urumqi
Period	20/07/19 → 22/07/19

Keywords

FIR digital filter
FPGA
Reconfigurable
Signal processing

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10.1007/978-981-13-9409-6_47

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Zhang, N., Wei, X., Li, B., & Chen, H. (2020). FPGA-Based Implementation of Reconfigurable Floating-Point FIR Digital Filter. In Q. Liang, W. Wang, X. Liu, Z. Na, M. Jia, & B. Zhang (Eds.), Communications, Signal Processing, and Systems - Proceedings of the 8th International Conference on Communications, Signal Processing, and Systems, CSPS 2019 (pp. 400-407). (Lecture Notes in Electrical Engineering; Vol. 571 LNEE). Springer. https://doi.org/10.1007/978-981-13-9409-6_47

Zhang, Ning ; Wei, Xin ; Li, Bingyi et al. / FPGA-Based Implementation of Reconfigurable Floating-Point FIR Digital Filter. Communications, Signal Processing, and Systems - Proceedings of the 8th International Conference on Communications, Signal Processing, and Systems, CSPS 2019. editor / Qilian Liang ; Wei Wang ; Xin Liu ; Zhenyu Na ; Min Jia ; Baoju Zhang. Springer, 2020. pp. 400-407 (Lecture Notes in Electrical Engineering).

@inproceedings{ad5bb3731d6a40929f44086461327a2e,

title = "FPGA-Based Implementation of Reconfigurable Floating-Point FIR Digital Filter",

abstract = "As a critical digital signal processing method, finite impulse response (FIR) digital filter is widely used in radar signal processing, synthetic aperture radar (SAR) signal processing, etc. Furthermore, an efficient FIR hardware implementation contributes to the practical application of these processing. However, as a computation-intensive operation, the multiple high order FIR digital filter consumes a lot of hardware resources when implemented in commonly used chips such as field-programmable gate array (FPGA). In this paper, a reconfigurable FIR digital filter architecture is presented, which can perform different order FIR filtering operation without FPGA re-programming. In the experiment, the proposed FIR digital filter architecture was implemented and validated on the Xilinx Zedboard Evaluation Kit. The experimental results demonstrate that this design has a low consumption of hardware resources and can achieve real-time processing performance for digital signal processing in the practical applications.",

keywords = "FIR digital filter, FPGA, Reconfigurable, Signal processing",

author = "Ning Zhang and Xin Wei and Bingyi Li and He Chen",

note = "Publisher Copyright: {\textcopyright} 2020, Springer Nature Singapore Pte Ltd.; 8th International Conference on Communications, Signal Processing, and Systems, CSPS 2019 ; Conference date: 20-07-2019 Through 22-07-2019",

year = "2020",

doi = "10.1007/978-981-13-9409-6_47",

language = "English",

isbn = "9789811394089",

series = "Lecture Notes in Electrical Engineering",

publisher = "Springer",

pages = "400--407",

editor = "Qilian Liang and Wei Wang and Xin Liu and Zhenyu Na and Min Jia and Baoju Zhang",

booktitle = "Communications, Signal Processing, and Systems - Proceedings of the 8th International Conference on Communications, Signal Processing, and Systems, CSPS 2019",

address = "Germany",

}

Zhang, N, Wei, X, Li, B & Chen, H 2020, FPGA-Based Implementation of Reconfigurable Floating-Point FIR Digital Filter. in Q Liang, W Wang, X Liu, Z Na, M Jia & B Zhang (eds), Communications, Signal Processing, and Systems - Proceedings of the 8th International Conference on Communications, Signal Processing, and Systems, CSPS 2019. Lecture Notes in Electrical Engineering, vol. 571 LNEE, Springer, pp. 400-407, 8th International Conference on Communications, Signal Processing, and Systems, CSPS 2019, Urumqi, China, 20/07/19. https://doi.org/10.1007/978-981-13-9409-6_47

FPGA-Based Implementation of Reconfigurable Floating-Point FIR Digital Filter. / Zhang, Ning; Wei, Xin; Li, Bingyi et al.
Communications, Signal Processing, and Systems - Proceedings of the 8th International Conference on Communications, Signal Processing, and Systems, CSPS 2019. ed. / Qilian Liang; Wei Wang; Xin Liu; Zhenyu Na; Min Jia; Baoju Zhang. Springer, 2020. p. 400-407 (Lecture Notes in Electrical Engineering; Vol. 571 LNEE).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - FPGA-Based Implementation of Reconfigurable Floating-Point FIR Digital Filter

AU - Zhang, Ning

AU - Wei, Xin

AU - Li, Bingyi

AU - Chen, He

PY - 2020

Y1 - 2020

N2 - As a critical digital signal processing method, finite impulse response (FIR) digital filter is widely used in radar signal processing, synthetic aperture radar (SAR) signal processing, etc. Furthermore, an efficient FIR hardware implementation contributes to the practical application of these processing. However, as a computation-intensive operation, the multiple high order FIR digital filter consumes a lot of hardware resources when implemented in commonly used chips such as field-programmable gate array (FPGA). In this paper, a reconfigurable FIR digital filter architecture is presented, which can perform different order FIR filtering operation without FPGA re-programming. In the experiment, the proposed FIR digital filter architecture was implemented and validated on the Xilinx Zedboard Evaluation Kit. The experimental results demonstrate that this design has a low consumption of hardware resources and can achieve real-time processing performance for digital signal processing in the practical applications.

AB - As a critical digital signal processing method, finite impulse response (FIR) digital filter is widely used in radar signal processing, synthetic aperture radar (SAR) signal processing, etc. Furthermore, an efficient FIR hardware implementation contributes to the practical application of these processing. However, as a computation-intensive operation, the multiple high order FIR digital filter consumes a lot of hardware resources when implemented in commonly used chips such as field-programmable gate array (FPGA). In this paper, a reconfigurable FIR digital filter architecture is presented, which can perform different order FIR filtering operation without FPGA re-programming. In the experiment, the proposed FIR digital filter architecture was implemented and validated on the Xilinx Zedboard Evaluation Kit. The experimental results demonstrate that this design has a low consumption of hardware resources and can achieve real-time processing performance for digital signal processing in the practical applications.

KW - FIR digital filter

KW - FPGA

KW - Reconfigurable

KW - Signal processing

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U2 - 10.1007/978-981-13-9409-6_47

DO - 10.1007/978-981-13-9409-6_47

M3 - Conference contribution

AN - SCOPUS:85084765499

SN - 9789811394089

T3 - Lecture Notes in Electrical Engineering

SP - 400

EP - 407

BT - Communications, Signal Processing, and Systems - Proceedings of the 8th International Conference on Communications, Signal Processing, and Systems, CSPS 2019

A2 - Liang, Qilian

A2 - Wang, Wei

A2 - Liu, Xin

A2 - Na, Zhenyu

A2 - Jia, Min

A2 - Zhang, Baoju

PB - Springer

T2 - 8th International Conference on Communications, Signal Processing, and Systems, CSPS 2019

Y2 - 20 July 2019 through 22 July 2019

ER -

Zhang N, Wei X, Li B, Chen H. FPGA-Based Implementation of Reconfigurable Floating-Point FIR Digital Filter. In Liang Q, Wang W, Liu X, Na Z, Jia M, Zhang B, editors, Communications, Signal Processing, and Systems - Proceedings of the 8th International Conference on Communications, Signal Processing, and Systems, CSPS 2019. Springer. 2020. p. 400-407. (Lecture Notes in Electrical Engineering). doi: 10.1007/978-981-13-9409-6_47

FPGA-Based Implementation of Reconfigurable Floating-Point FIR Digital Filter

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