Design and implementation of the on-line configurable digital down converter (DDC) based on FPGA

An on-line reconfigurable DDC of FPGA is designed and implemented in this research. It could produce automatically the optimal DDC structure and DDC parameters by utilizing 3 parameters of the input signal (the frequency, the bandwidth and the sampling rate of IF signal). A new kind of optimal finite impulse response(FIR) filter was designed. Employing the property of linear phase and coefficient symmetry and using pre-add method, the optimal FIR filter could reduce half as the amount of the multiplication computation as the traditional FIR filter. Therefore, the balance between the resource occupation ratio and speed could be realized and it helps saving the FPGA resources. Experimental results show the flexibility and effectiveness of the presented method.