@inproceedings{f2c6771569744a26a6a93a06cee1c784,
title = "A W-Band Power Amplifier With 19.6% PAE in 45-nm SOI CMOS",
abstract = "This paper presents a two-way power-combing W-band power amplifier (PA) in 45nm SOI CMOS process. To alleviate the parasitism in large-sized transistors, the customized power cell with an optimized layout is adopted. The drain-gate neutralized common-source (CS) stages are employed in the two amplification stages of the PA to enhance power gain and guarantee stability. Two types of transform-based power combining are analyzed and compared. Parallel combining is considered more suitable in this design for a lower transformation ratio and higher power-combining efficiency. The PA is designed and achieves 11.7-dBm output 1-dB compression point (P1dB), 15.2-dBm saturated output power (Psat), and 19.6% power added efficiency (PAE) at 94GHz. The 3-dB bandwidth of the PA is from 85-105GHz.",
keywords = "CMOS, Power amplifier (PA), W-band, capacitive neutralization, power combining",
author = "Shutian Cai and Zhiming Chen and Xiaoran Li and Zicheng Liu and Fang Han and Quanwen Qi and Xinghua Wang",
note = "Publisher Copyright: {\textcopyright} 2024 IEEE.; 7th IEEE Advanced Information Technology, Electronic and Automation Control Conference, IAEAC 2024 ; Conference date: 15-03-2024 Through 17-03-2024",
year = "2024",
doi = "10.1109/IAEAC59436.2024.10503840",
language = "English",
series = "IEEE Advanced Information Technology, Electronic and Automation Control Conference (IAEAC)",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "1896--1900",
editor = "Bing Xu",
booktitle = "IAEAC 2024 - IEEE 7th Advanced Information Technology, Electronic and Automation Control Conference",
address = "United States",
}