A hybrid high-performance embedded processing system

Yi Deng*, Teng Long

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

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Abstract

In this paper, we analyze the speedup formula, and expand the formula in detail. After discuss the timing problems of parallel computing, we give some designing rules, specially applied to HPEC (high-performance embedded computing) systems. Further analyzing the characteristics of HPEC system, a modular processing architecture is proposed. Due to the development of interconnection technologies, we design a type of hybrid PE (Processing Element) architecture, and describe the compositions of the PE. The implementation methods of the hybrid PE are described. An actual platform is established to certity the feasibility and performance of the system.

Original languageEnglish
Title of host publication2010 2nd International Conference on Industrial Mechatronics and Automation, ICIMA 2010
Pages256-259
Number of pages4
DOIs
Publication statusPublished - 2010
Event2010 2nd International Conference on Industrial Mechatronics and Automation, ICIMA 2010 - Wuhan, China
Duration: 30 May 201031 May 2010

Publication series

NameICIMA 2010 - 2010 2nd International Conference on Industrial Mechatronics and Automation
Volume2

Conference

Conference2010 2nd International Conference on Industrial Mechatronics and Automation, ICIMA 2010
Country/TerritoryChina
CityWuhan
Period30/05/1031/05/10

Keywords

  • Embedded
  • Hybrid processing
  • Parallel architecture
  • Real-time computing
  • Signal processing

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Deng, Y., & Long, T. (2010). A hybrid high-performance embedded processing system. In 2010 2nd International Conference on Industrial Mechatronics and Automation, ICIMA 2010 (pp. 256-259). Article 5538322 (ICIMA 2010 - 2010 2nd International Conference on Industrial Mechatronics and Automation; Vol. 2). https://doi.org/10.1109/ICINDMA.2010.5538322