摘要
To address performance and accuracy problems caused by synchronization as simulating a many-core computer in parallel, two-level synchronous mechanism is proposed. The first level synchronization functioning among all nodes ensures the global time order. The second level synchronization maintains the time order between high level caches and the NoC (Network on Chip) router on one node, which improves parallelism without hurting fidelity of models. The theoretical analysis reveals the upper and lower bounds on the performance of proposed mechanism. And the experiment shows it obtains good speed-up and reasonable scalability.
| 源语言 | 英语 |
|---|---|
| 页（从-至） | 2806-2813 |
| 页数 | 8 |
| 期刊 | Xitong Fangzhen Xuebao / Journal of System Simulation |
| 卷 | 25 |
| 期 | 12 |
| 出版状态 | 已出版 - 12月 2013 |
| 已对外发布 | 是 |