@inproceedings{bde3823c001342168880e85b90a49488,
title = "Tracking radar digital matched-filter ASIC design and its error analysis",
abstract = "The matched-filter is widely used in real time signal processing, especially in radar signal processing. This paper presents a novel structure of a digital tracking radar matched-filter, whose hardware overhead is one third of the traditional design but its throughput is doubled. With block-floating-point arithmetic, the precision is highly improved. The whole digital matched-filter is implemented in just one FPGA chip. This ASIC has two work modes: 512 points pulse compression and 256 points pulse compression. It complements three channels of 512 points complex signals in 102 μs. The signal-to-noise ratio formula of this matched-filter is deduced at the end of the paper.",
keywords = "Application specific integrated circuits, Arithmetic, Error analysis, Field programmable gate arrays, Hardware, Pulse compression methods, Radar signal processing, Radar tracking, Signal to noise ratio, Throughput",
author = "Zhenyu Liu and Zhimei Zhou and Yueqiu Han",
note = "Publisher Copyright: {\textcopyright} 2002 IEEE.; Asia-Pacific Conference on Circuits and Systems, APCCAS 2002 ; Conference date: 28-10-2002 Through 31-10-2002",
year = "2002",
doi = "10.1109/APCCAS.2002.1115039",
language = "English",
series = "IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "491--496",
booktitle = "Proceedings - APCCAS 2002",
address = "United States",
}