摘要
The matched-filter is widely used in real time signal processing, especially in radar signal processing. This paper presents a novel structure of a digital tracking radar matched-filter, whose hardware overhead is one third of the traditional design but its throughput is doubled. With block-floating-point arithmetic, the precision is highly improved. The whole digital matched-filter is implemented in just one FPGA chip. This ASIC has two work modes: 512 points pulse compression and 256 points pulse compression. It complements three channels of 512 points complex signals in 102 μs. The signal-to-noise ratio formula of this matched-filter is deduced at the end of the paper.
| 源语言 | 英语 |
|---|---|
| 主期刊名 | Proceedings - APCCAS 2002 |
| 主期刊副标题 | Asia-Pacific Conference on Circuits and Systems |
| 出版商 | Institute of Electrical and Electronics Engineers Inc. |
| 页 | 491-496 |
| 页数 | 6 |
| ISBN（电子版） | 0780376900 |
| DOI | |
| 出版状态 | 已出版 - 2002 |
| 活动 | Asia-Pacific Conference on Circuits and Systems, APCCAS 2002 - Denpasar, Bali, 印度尼西亚 期限: 28 10月 2002 → 31 10月 2002 |
出版系列
| 姓名 | IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS |
|---|---|
| 卷 | 1 |
会议
| 会议 | Asia-Pacific Conference on Circuits and Systems, APCCAS 2002 |
|---|---|
| 国家/地区 | 印度尼西亚 |
| 市 | Denpasar, Bali |
| 时期 | 28/10/02 → 31/10/02 |
指纹
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Liu, Z., Zhou, Z., & Han, Y. (2002). Tracking radar digital matched-filter ASIC design and its error analysis. 在 Proceedings - APCCAS 2002: Asia-Pacific Conference on Circuits and Systems (页码 491-496). 文章 1115039 (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS; 卷 1). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/APCCAS.2002.1115039