TY - JOUR
T1 - Time-varying network architecture of fractional multiple sampling rate converter and its FPGA implementation
AU - Li, Ju
AU - Chen, He
AU - He, Pei Kun
AU - Wu, Si Liang
PY - 2005/9
Y1 - 2005/9
N2 - The design method for the efficient time-varying network architecture of the fractional multiple sampling rate converter is presented and its field programmable gate array (FPGA) is implemented. Compared the polyphase architecture with the time-varying network architecture of the fractional multiple sampling rate converter, the time-varying architecture overcomes a fractional delay problem when implementing the fractional multiple sampling rate converter, and so its structure is simple. This design for the parallel pipeline structure is used to improve the processing speed. The operated filtering at a low sampling rate can reduce the count quantity. When the fractional multiple sampling rate is I/D= 256/1023, the whole design is implemented with one chip of XC2V250-5 FPGA, the use factor of the chip is 61% and the maximum frequency is 92.225 MHz. The design is verified by simulation and measurement results.
AB - The design method for the efficient time-varying network architecture of the fractional multiple sampling rate converter is presented and its field programmable gate array (FPGA) is implemented. Compared the polyphase architecture with the time-varying network architecture of the fractional multiple sampling rate converter, the time-varying architecture overcomes a fractional delay problem when implementing the fractional multiple sampling rate converter, and so its structure is simple. This design for the parallel pipeline structure is used to improve the processing speed. The operated filtering at a low sampling rate can reduce the count quantity. When the fractional multiple sampling rate is I/D= 256/1023, the whole design is implemented with one chip of XC2V250-5 FPGA, the use factor of the chip is 61% and the maximum frequency is 92.225 MHz. The design is verified by simulation and measurement results.
KW - Field programmable gate array
KW - Fractional multiple sampling rate converter
KW - Polyphase architecture
KW - Time-varying network architecture
UR - http://www.scopus.com/inward/record.url?scp=27244454131&partnerID=8YFLogxK
M3 - Article
AN - SCOPUS:27244454131
SN - 1004-9037
VL - 20
SP - 268
EP - 271
JO - Shuju Caiji Yu Chuli/Journal of Data Acquisition and Processing
JF - Shuju Caiji Yu Chuli/Journal of Data Acquisition and Processing
IS - 3
ER -