Time-varying network architecture of fractional multiple sampling rate converter and its FPGA implementation

Ju Li*, He Chen, Pei Kun He, Si Liang Wu

*此作品的通讯作者

科研成果: 期刊稿件文章同行评审

1 引用 (Scopus)

摘要

The design method for the efficient time-varying network architecture of the fractional multiple sampling rate converter is presented and its field programmable gate array (FPGA) is implemented. Compared the polyphase architecture with the time-varying network architecture of the fractional multiple sampling rate converter, the time-varying architecture overcomes a fractional delay problem when implementing the fractional multiple sampling rate converter, and so its structure is simple. This design for the parallel pipeline structure is used to improve the processing speed. The operated filtering at a low sampling rate can reduce the count quantity. When the fractional multiple sampling rate is I/D= 256/1023, the whole design is implemented with one chip of XC2V250-5 FPGA, the use factor of the chip is 61% and the maximum frequency is 92.225 MHz. The design is verified by simulation and measurement results.

源语言英语
页(从-至)268-271
页数4
期刊Shuju Caiji Yu Chuli/Journal of Data Acquisition and Processing
20
3
出版状态已出版 - 9月 2005

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