The Reconfigurable Pipelined Variable-point FFT Processor Design

Jiale Wang; Yizhuang Xie; Bingyi Li; Chen Yang; Shankang Hu

doi:10.1109/ICSIDP47821.2019.9172930

The Reconfigurable Pipelined Variable-point FFT Processor Design

Jiale Wang, Yizhuang Xie, Bingyi Li, Chen Yang, Shankang Hu

信息与电子学院

Beijing Institute of Technology

科研成果: 书/报告/会议事项章节 › 会议稿件 › 同行评审

2 引用（Scopus）

摘要

In the multi-mode SAR imaging processing targeted in this paper, the FFT requirement granularity ranges from 1024 to 32768. Therefore, this paper mainly describes the method of implementing reconfigurable and variable-level FFT units using radix-2^k, By analyzing and comparing the radix 2^k algorithm, the radix-2³ is selected as the basis of the single-channel FFT butterfly, and the range of the point representation is extended by the butterfly transformation downward compatible with the radix-2²/radix-2. This paper realizes an architecture of the single channel delay feedback variable-point, high precision FFT processor.

源语言	英语
主期刊名	ICSIDP 2019 - IEEE International Conference on Signal, Information and Data Processing 2019
出版商	Institute of Electrical and Electronics Engineers Inc.
ISBN（电子版）	9781728123455
DOI	https://doi.org/10.1109/ICSIDP47821.2019.9172930
出版状态	已出版 - 12月 2019
活动	2019 IEEE International Conference on Signal, Information and Data Processing, ICSIDP 2019 - Chongqing, 中国期限: 11 12月 2019 → 13 12月 2019

出版系列

姓名	ICSIDP 2019 - IEEE International Conference on Signal, Information and Data Processing 2019

会议

会议	2019 IEEE International Conference on Signal, Information and Data Processing, ICSIDP 2019
国家/地区	中国
市	Chongqing
时期	11/12/19 → 13/12/19

访问文件

10.1109/ICSIDP47821.2019.9172930

其它文件与链接

链接到 Scopus 的出版物

引用此

Wang, J., Xie, Y., Li, B., Yang, C., & Hu, S. (2019). The Reconfigurable Pipelined Variable-point FFT Processor Design. 在 ICSIDP 2019 - IEEE International Conference on Signal, Information and Data Processing 2019 文章 9172930 (ICSIDP 2019 - IEEE International Conference on Signal, Information and Data Processing 2019). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICSIDP47821.2019.9172930

@inproceedings{08a29128d7504dcb8cc7c87c20284e50,

title = "The Reconfigurable Pipelined Variable-point FFT Processor Design",

abstract = "In the multi-mode SAR imaging processing targeted in this paper, the FFT requirement granularity ranges from 1024 to 32768. Therefore, this paper mainly describes the method of implementing reconfigurable and variable-level FFT units using radix-2k, By analyzing and comparing the radix 2k algorithm, the radix-23 is selected as the basis of the single-channel FFT butterfly, and the range of the point representation is extended by the butterfly transformation downward compatible with the radix-22/radix-2. This paper realizes an architecture of the single channel delay feedback variable-point, high precision FFT processor.",

keywords = "FFT, floating-point, pipelined, reconfigurable, single delay feedback, variable-radix",

author = "Jiale Wang and Yizhuang Xie and Bingyi Li and Chen Yang and Shankang Hu",

note = "Publisher Copyright: {\textcopyright} 2019 IEEE.; 2019 IEEE International Conference on Signal, Information and Data Processing, ICSIDP 2019 ; Conference date: 11-12-2019 Through 13-12-2019",

year = "2019",

month = dec,

doi = "10.1109/ICSIDP47821.2019.9172930",

language = "English",

series = "ICSIDP 2019 - IEEE International Conference on Signal, Information and Data Processing 2019",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "ICSIDP 2019 - IEEE International Conference on Signal, Information and Data Processing 2019",

address = "United States",

}

Wang, J, Xie, Y, Li, B, Yang, C & Hu, S 2019, The Reconfigurable Pipelined Variable-point FFT Processor Design. 在 ICSIDP 2019 - IEEE International Conference on Signal, Information and Data Processing 2019., 9172930, ICSIDP 2019 - IEEE International Conference on Signal, Information and Data Processing 2019, Institute of Electrical and Electronics Engineers Inc., 2019 IEEE International Conference on Signal, Information and Data Processing, ICSIDP 2019, Chongqing, 中国, 11/12/19. https://doi.org/10.1109/ICSIDP47821.2019.9172930

The Reconfigurable Pipelined Variable-point FFT Processor Design. / Wang, Jiale; Xie, Yizhuang; Li, Bingyi 等.
ICSIDP 2019 - IEEE International Conference on Signal, Information and Data Processing 2019. Institute of Electrical and Electronics Engineers Inc., 2019. 9172930 (ICSIDP 2019 - IEEE International Conference on Signal, Information and Data Processing 2019).

科研成果: 书/报告/会议事项章节 › 会议稿件 › 同行评审

TY - GEN

T1 - The Reconfigurable Pipelined Variable-point FFT Processor Design

AU - Wang, Jiale

AU - Xie, Yizhuang

AU - Li, Bingyi

AU - Yang, Chen

AU - Hu, Shankang

PY - 2019/12

Y1 - 2019/12

N2 - In the multi-mode SAR imaging processing targeted in this paper, the FFT requirement granularity ranges from 1024 to 32768. Therefore, this paper mainly describes the method of implementing reconfigurable and variable-level FFT units using radix-2k, By analyzing and comparing the radix 2k algorithm, the radix-23 is selected as the basis of the single-channel FFT butterfly, and the range of the point representation is extended by the butterfly transformation downward compatible with the radix-22/radix-2. This paper realizes an architecture of the single channel delay feedback variable-point, high precision FFT processor.

AB - In the multi-mode SAR imaging processing targeted in this paper, the FFT requirement granularity ranges from 1024 to 32768. Therefore, this paper mainly describes the method of implementing reconfigurable and variable-level FFT units using radix-2k, By analyzing and comparing the radix 2k algorithm, the radix-23 is selected as the basis of the single-channel FFT butterfly, and the range of the point representation is extended by the butterfly transformation downward compatible with the radix-22/radix-2. This paper realizes an architecture of the single channel delay feedback variable-point, high precision FFT processor.

KW - FFT

KW - floating-point

KW - pipelined

KW - reconfigurable

KW - single delay feedback

KW - variable-radix

UR - http://www.scopus.com/inward/record.url?scp=85091909251&partnerID=8YFLogxK

U2 - 10.1109/ICSIDP47821.2019.9172930

DO - 10.1109/ICSIDP47821.2019.9172930

M3 - Conference contribution

AN - SCOPUS:85091909251

T3 - ICSIDP 2019 - IEEE International Conference on Signal, Information and Data Processing 2019

BT - ICSIDP 2019 - IEEE International Conference on Signal, Information and Data Processing 2019

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2019 IEEE International Conference on Signal, Information and Data Processing, ICSIDP 2019

Y2 - 11 December 2019 through 13 December 2019

ER -

Wang J, Xie Y, Li B, Yang C, Hu S. The Reconfigurable Pipelined Variable-point FFT Processor Design. 在 ICSIDP 2019 - IEEE International Conference on Signal, Information and Data Processing 2019. Institute of Electrical and Electronics Engineers Inc. 2019. 9172930. (ICSIDP 2019 - IEEE International Conference on Signal, Information and Data Processing 2019). doi: 10.1109/ICSIDP47821.2019.9172930

The Reconfigurable Pipelined Variable-point FFT Processor Design

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