Small-scale CMOS pseudo SRAM module design

Yun Li*, Zhen Yu Liu, Yue Qiu Han

*此作品的通讯作者

科研成果: 期刊稿件文章同行评审

摘要

An approach to design small scale CMOS static random access memory (SRAM) is proposed. The design of address decoder, memory cell, and the layout are included. This approach adopts flip-flop array structure. The flip-flops are used as the storage cells and they are stacked to form the whole SRAM module. The word select bit is generated from the address decoder. And one word at a time is selected for reading or writing. The design of the memory core's layout is also discussed since it should be optimized to save area and also should be convenient for realization. It's a full-custom layout. The address decoder is composed of combinational logic circuit and its layout is also designed as a full-custom layout. With all these modules, the integral structure of the SRAM is carried out.

源语言英语
页(从-至)127-130
页数4
期刊Journal of Beijing Institute of Technology (English Edition)
13
2
出版状态已出版 - 6月 2004

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