摘要
A register translation level (RTL) module design method of Data-RAM for double precision float-point digital signal processor is proposed. Structure and accessing principles of Data-RAM are studied. By using top down method and VHDL, RTL module is designed and the correctness of function confirmed. This RTL module supports access in three addresses independently. The access modes include byte, half word, word and double word. Two 64 bit data can be read and one 32 bit data can be written or read in one clock cycle, if accesses do not conflict. The design of Data-RAM on gates level and physical level can be directed by this RTL module.
| 源语言 | 英语 |
|---|---|
| 页（从-至） | 68-72 |
| 页数 | 5 |
| 期刊 | Beijing Ligong Daxue Xuebao/Transaction of Beijing Institute of Technology |
| 卷 | 27 |
| 期 | 1 |
| 出版状态 | 已出版 - 1月 2007 |