Rapid acquisition for direct sequence spread-spectrum signals

A new improved architecture to realize rapid acquisition for direct sequence spread-spectrum signals was presented. To reduce hardware resources, this architecture utilized duplicate design to realize FFT and IFFT in the same unit and calculated the FFT of local code by software and stored it in ROM; this design applied parallel pipeline structure to improve the processing speed; block floating-point arithmetic was used to enhance the dynamic range and computation accuracy. The whole design was implemented with only one chip of XC2V3000-5 FPGA. When working clock was 29 ns and acquisition precision was 1/4 code, the acquisition time would be within 4.145 ms. The validity of design is verified by simulation and measurement results.