TY - GEN
T1 - Programmable On-Chip Photonic Signal Processor Based on a Microdisk Resonator Array
AU - Zhang, Weifeng
AU - Yao, Jianping
N1 - Publisher Copyright:
© 2018 IEEE.
PY - 2018/11/29
Y1 - 2018/11/29
N2 - A programmable on-chip photonic signal processor based on a silicon photonic microdisk resonator array is proposed and experimentally demonstrated. The processor has a two-dimensional mesh network structure with multiple input and multiple output ports. In each mesh cell, two identical thermally-tunable high-Q microdisk resonators (MDRs) are used for routing and processing the optical signal, and a low-loss waveguide crossing is employed at the waveguide intersection to enable low-crosstalk optical transmission. By programming the DC voltages applied to the MDRs, the processor can be reconfigured with diverse circuit topologies to perform multiple array signal processing functions. An 8 × 8 programmable signal processor is designed, fabricated and characterized. By controlling the DC voltages, an on-chip tunable optical delay line based on 8 MDRs cascaded in an all-pass filter configuration is experimentally demonstrated. Thanks to scalable mesh structure of the proposed processor, the entire device holds a promising potential for strong reconfigurability and parallel computing with low power consumption.
AB - A programmable on-chip photonic signal processor based on a silicon photonic microdisk resonator array is proposed and experimentally demonstrated. The processor has a two-dimensional mesh network structure with multiple input and multiple output ports. In each mesh cell, two identical thermally-tunable high-Q microdisk resonators (MDRs) are used for routing and processing the optical signal, and a low-loss waveguide crossing is employed at the waveguide intersection to enable low-crosstalk optical transmission. By programming the DC voltages applied to the MDRs, the processor can be reconfigured with diverse circuit topologies to perform multiple array signal processing functions. An 8 × 8 programmable signal processor is designed, fabricated and characterized. By controlling the DC voltages, an on-chip tunable optical delay line based on 8 MDRs cascaded in an all-pass filter configuration is experimentally demonstrated. Thanks to scalable mesh structure of the proposed processor, the entire device holds a promising potential for strong reconfigurability and parallel computing with low power consumption.
KW - optical delay line
KW - photonic processing of microwave signals
KW - silicon photonics
UR - http://www.scopus.com/inward/record.url?scp=85060017795&partnerID=8YFLogxK
U2 - 10.1109/MWP.2018.8552873
DO - 10.1109/MWP.2018.8552873
M3 - Conference contribution
AN - SCOPUS:85060017795
T3 - MWP 2018 - 2018 International Topical Meeting on Microwave Photonics
BT - MWP 2018 - 2018 International Topical Meeting on Microwave Photonics
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2018 International Topical Meeting on Microwave Photonics, MWP 2018
Y2 - 22 October 2018 through 25 October 2018
ER -