Noise and Spur Comparison of Delta-Sigma Modulators in Fractional-N PLLs

A fractional-N phase-locked loop (PLL) with four kinds of delta-sigma modulators (DSMs), is implemented to analyze and compare PLL phase noise and fractional spur performances among different DSMs, including 4^th- and 5^th-order single-loop (SL) and 3^rd- and 4^th-order multi-stage noise-shaping (MASH) ones. SL-DSMs with fewer output levels resulting in smaller instantaneous phase error, achieve better phase noise. MASH DSMs with wider quantization levels having more efficient randomization and dithering effects, generate less fractional spur. Experimental results show that in-band and out-of-band fractional spurs of MASH DSM are 10.5 and 5.8dB better than those of SL-DSM, respectively, while out-of-band phase noise of SL-DSM is 4.5dB lower than that of MASH DSM, with the same order. The fractional-N PLL is fabricated in 180nm CMOS with a 1.8V supply voltage and power consumption of approximately 23mW.