@inproceedings{4c147e1e2af7457eb8f537207f3865cc,
title = "NoBapCL: A flexible common language for processor hardware description",
abstract = "Flexible Application Specific Instruction set Processors (ASIP) are starting to replace monolithic ASICs in a wide variety of fields. However the construction of an ASIP is today associated with a substantial design effort. NoBap (Novel Generator of Micro Architecture and Processor) is a tool for ASIP designs, utilizing hardware multiplexed data paths. One of the main advantages of NoBap compared to other EDA tools for processor design, is that NoBap impose few limits on the architecture and thus design freedom. NoBap does not assume a fixed processor template and is not a data flow synthesizer. To reach this flexibility NoBap makes heavy use of the compositional design principle. This paper describe NoBapCL, a flexible common language for processor hardware description. A RISC processor using NoBapCL has been constructed with NoBap in less than a working day and synthesized to an FPGA. With no FPGA specific optimizations this processor met timing closure at 178MHz in a Virtex-4 LX80 speedgrade 12.",
keywords = "ADL, ASIP, CAD",
author = "Wenbiao Zhou and Per Karlstr{\"o}m and Dake Liu",
year = "2010",
doi = "10.1109/DDECS.2010.5491778",
language = "English",
isbn = "9781424466139",
series = "Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010",
pages = "225--228",
booktitle = "Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010",
note = "13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010 ; Conference date: 14-04-2010 Through 16-04-2010",
}
