TY - GEN
T1 - MALsim
T2 - 2010 2nd International Conference on Computer Engineering and Technology, ICCET 2010
AU - Sui, Xiufeng
AU - Wu, Junmin
AU - Yin, Wei
AU - Zhou, Dapeng
AU - Gong, Zhe
PY - 2010
Y1 - 2010
N2 - Computer system simulation, including both functional level and cycle accurate level, is a crucial method for computer architecture design. And functional simulation is also called simulator kernel. It is built as an autonomous library and provides an interface to the rest of the simulator [1, 2, 3]. And it's really important for system verification and system software development. However, as the approaching of the multi-core era, the fast simulation of chip multiprocessors (CMPs) is becoming a critical challenge to the architecture research community, since the speed of functional simulator suffers from superlinear slowdown as the number of cores increases. Parallel simulation is an efficient way to accelerate architecture simulation of CMPs. In this paper, we implement a parallel functional simulator called MALsim. Our work can be divided into two parts: 1) the parallelization based on multiprogrammed workloads, and 2) the parallelization based on multithreaded workloads. We implement the parallel functional simulator using POSIX threads on a multi-core host system. The evaluations show that our MALsim kernel can reach the average speedup of 1.748, 3.644, 7.372, 15.628 with 2, 4, 8, 16 threads respectively when running multiprogrammed workloads, and it will achieve the average speedup of 1.692, 2.76, 3.833, 5.292 with 2, 4, 8, 16 threads respectively when running multithreaded workloads.
AB - Computer system simulation, including both functional level and cycle accurate level, is a crucial method for computer architecture design. And functional simulation is also called simulator kernel. It is built as an autonomous library and provides an interface to the rest of the simulator [1, 2, 3]. And it's really important for system verification and system software development. However, as the approaching of the multi-core era, the fast simulation of chip multiprocessors (CMPs) is becoming a critical challenge to the architecture research community, since the speed of functional simulator suffers from superlinear slowdown as the number of cores increases. Parallel simulation is an efficient way to accelerate architecture simulation of CMPs. In this paper, we implement a parallel functional simulator called MALsim. Our work can be divided into two parts: 1) the parallelization based on multiprogrammed workloads, and 2) the parallelization based on multithreaded workloads. We implement the parallel functional simulator using POSIX threads on a multi-core host system. The evaluations show that our MALsim kernel can reach the average speedup of 1.748, 3.644, 7.372, 15.628 with 2, 4, 8, 16 threads respectively when running multiprogrammed workloads, and it will achieve the average speedup of 1.692, 2.76, 3.833, 5.292 with 2, 4, 8, 16 threads respectively when running multithreaded workloads.
KW - Architectural simulation
KW - Chip multiprocessors
KW - Parallel simulation
UR - http://www.scopus.com/inward/record.url?scp=77958056574&partnerID=8YFLogxK
U2 - 10.1109/ICCET.2010.5485532
DO - 10.1109/ICCET.2010.5485532
M3 - Conference contribution
AN - SCOPUS:77958056574
SN - 9781424463503
T3 - ICCET 2010 - 2010 International Conference on Computer Engineering and Technology, Proceedings
SP - V2440-V2444
BT - ICCET 2010 - 2010 International Conference on Computer Engineering and Technology, Proceedings
Y2 - 16 April 2010 through 18 April 2010
ER -