TY - GEN
T1 - Low-Temperature Fabrication of Solution-Processed InGaZnO Thin-Film Transistors
AU - Chen, Yonghua
AU - Yu, Zhinong
AU - Li, Xuyang
AU - Cheng, Jin
N1 - Publisher Copyright:
© 2018 IEEE.
PY - 2019/1/10
Y1 - 2019/1/10
N2 - We report a novel method for fabricating solution-processed quaternary In-Ga-Zn-O (IGZO) thin-film transistors (TFTs) at low annealing temperature. The method is to spin coat such binary oxide layers as Ga 2 O 3 , ZnO and In 2 O 3 consecutively and then anneal the layers at 250 °C. Finally, due to vertical diffusion of the binary oxides, the IGZO film with a vertically gradient In, Ga, Zn distribution (defined as vd-IGZO) is obtained and used as the channel layer of TFT. Compared with conventional IGZO (con-IGZO) TFTs annealing at 380°C, the vd-IGZO TFTs have better electrical performances.
AB - We report a novel method for fabricating solution-processed quaternary In-Ga-Zn-O (IGZO) thin-film transistors (TFTs) at low annealing temperature. The method is to spin coat such binary oxide layers as Ga 2 O 3 , ZnO and In 2 O 3 consecutively and then anneal the layers at 250 °C. Finally, due to vertical diffusion of the binary oxides, the IGZO film with a vertically gradient In, Ga, Zn distribution (defined as vd-IGZO) is obtained and used as the channel layer of TFT. Compared with conventional IGZO (con-IGZO) TFTs annealing at 380°C, the vd-IGZO TFTs have better electrical performances.
KW - low-temperature preparation
KW - thin-film transistors
UR - http://www.scopus.com/inward/record.url?scp=85061920143&partnerID=8YFLogxK
U2 - 10.1109/CAD-TFT.2018.8608055
DO - 10.1109/CAD-TFT.2018.8608055
M3 - Conference contribution
AN - SCOPUS:85061920143
T3 - 2018 9th International Conference on Computer Aided Design for Thin-Film Transistor Technologies, CAD-TFT 2018
BT - 2018 9th International Conference on Computer Aided Design for Thin-Film Transistor Technologies, CAD-TFT 2018
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 9th International Conference on Computer Aided Design for Thin-Film Transistor Technologies, CAD-TFT 2018
Y2 - 16 November 2018 through 18 November 2018
ER -