TY - JOUR
T1 - Low-energy complementary ferroelectric-nanocrack logic
AU - Guo, Zhe
AU - Luo, Qiang
AU - Huang, Houbing
AU - Zhang, Shuai
AU - Shi, Xiaoming
AU - Sun, Fei
AU - Ji, Yanzhou
AU - Zou, Qiming
AU - Song, Min
AU - Yang, Xiaofei
AU - Chen, Deyang
AU - Hong, Jeongmin
AU - Chen, Long Qing
AU - You, Long
N1 - Publisher Copyright:
© 2020 Elsevier Ltd
PY - 2020/9
Y1 - 2020/9
N2 - Ferroelectric-based electronic devices have excellent low-energy characteristics due to the highly insulating property, in which the Joule heating can be neglected. The recent discovery of electrically switchable cracks in ferroelectric/alloy film heterostructure gave rise to a new way to construct transistor, where the opening and closing of crack switched the channel current off and on. Here, we observed the complementary switching of cracks for the first time, and demonstrated a complementary inverter without any additional process to set different types of transistors, which was implemented by forming the n- and p-type transistor in conventional complementary metal oxide semiconductor (CMOS) technology. The complementary states were generated spontaneously once the cracks were induced and varied with the change of applied input voltage polarity. The low ON resistance and near-zero OFF state leakage current result in the high current on/off ratio (~107) and allow for the low dynamic and static power dissipation. Further, the switching of cracks is coupled to the surrounding ferroelectric polarization states, offering the non-destructive readout operation. We believe that our work provides a very simple route to build complementary logic gates and paves a way for the energy-efficient electronic devices, while promoting the “crack nanoelectronics”.
AB - Ferroelectric-based electronic devices have excellent low-energy characteristics due to the highly insulating property, in which the Joule heating can be neglected. The recent discovery of electrically switchable cracks in ferroelectric/alloy film heterostructure gave rise to a new way to construct transistor, where the opening and closing of crack switched the channel current off and on. Here, we observed the complementary switching of cracks for the first time, and demonstrated a complementary inverter without any additional process to set different types of transistors, which was implemented by forming the n- and p-type transistor in conventional complementary metal oxide semiconductor (CMOS) technology. The complementary states were generated spontaneously once the cracks were induced and varied with the change of applied input voltage polarity. The low ON resistance and near-zero OFF state leakage current result in the high current on/off ratio (~107) and allow for the low dynamic and static power dissipation. Further, the switching of cracks is coupled to the surrounding ferroelectric polarization states, offering the non-destructive readout operation. We believe that our work provides a very simple route to build complementary logic gates and paves a way for the energy-efficient electronic devices, while promoting the “crack nanoelectronics”.
KW - Complementary logic
KW - Ferroelectric device
KW - Low-energy electronics
KW - Nanocrack
KW - Non-destructive readout
KW - Phase-field simulation
UR - http://www.scopus.com/inward/record.url?scp=85085940515&partnerID=8YFLogxK
U2 - 10.1016/j.nanoen.2020.104871
DO - 10.1016/j.nanoen.2020.104871
M3 - Article
AN - SCOPUS:85085940515
SN - 2211-2855
VL - 75
JO - Nano Energy
JF - Nano Energy
M1 - 104871
ER -