Key techniques of VHDL parser's automatic generation

Zhendong Niu; Hantao Song; Mingye Liu

Key techniques of VHDL parser's automatic generation

Zhendong Niu^*, Hantao Song, Mingye Liu

^*此作品的通讯作者

计算机学院

Beijing Institute of Technology

科研成果: 期刊稿件 › 文章 › 同行评审

1 引用（Scopus）

摘要

VHDL and its supporting environment are an active domain in the field of logic design. In this paper the design principle and some key techniques to solve the problems on the implementation of the VHDL parser are introduced. According to the methods discussed in the paper, the VHDL parser based on VHDL IEEE 1076 standard version is implemented and a series of strict tests are done. This VHDL parser is a front-end tool of the VHDL high level synthesis and the mixed level simulation system developed by the Research Center of ASIC of BIT.

源语言	英语
页（从-至）	182-187
页数	6
期刊	Journal of Beijing Institute of Technology (English Edition)
卷	4
期	2
出版状态	已出版 - 12月 1995

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Niu, Z., Song, H., & Liu, M. (1995). Key techniques of VHDL parser's automatic generation. Journal of Beijing Institute of Technology (English Edition), 4(2), 182-187.

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Key techniques of VHDL parser's automatic generation

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