TY - JOUR
T1 - Implementation of a kind of FPGA-based binary phase coded radar signal processor architecture
AU - Tian, Li Yu
AU - Sun, Mi
AU - Wan, Yang Liang
PY - 2012/12
Y1 - 2012/12
N2 - A flexible field programmable gate array based radar signal processor is presented. The radar signal processor mainly consists of five functional modules: radar system timer, binary phase coded pulse compression(PC), moving target detection(MTD), constant false alarm rate(CFAR) and target dots processing. Preliminary target dots information is obtained in PC, MTD, and CFAR modules and Nios II CPU is used for target dots combination and false sidelobe target removing. System on programmable chip(SOPC) technique is adopted in the system in which SDRAM is used to cache data. Finally, a FPGA-based binary phase coded radar signal processor is realized and simulation result is given.
AB - A flexible field programmable gate array based radar signal processor is presented. The radar signal processor mainly consists of five functional modules: radar system timer, binary phase coded pulse compression(PC), moving target detection(MTD), constant false alarm rate(CFAR) and target dots processing. Preliminary target dots information is obtained in PC, MTD, and CFAR modules and Nios II CPU is used for target dots combination and false sidelobe target removing. System on programmable chip(SOPC) technique is adopted in the system in which SDRAM is used to cache data. Finally, a FPGA-based binary phase coded radar signal processor is realized and simulation result is given.
KW - Binary phase coded
KW - Field programmable gate array(FPGA)
KW - Radar signal processor
KW - System on programmable chip(SOPC)
UR - http://www.scopus.com/inward/record.url?scp=84873175266&partnerID=8YFLogxK
M3 - Article
AN - SCOPUS:84873175266
SN - 1004-0579
VL - 21
SP - 526
EP - 531
JO - Journal of Beijing Institute of Technology (English Edition)
JF - Journal of Beijing Institute of Technology (English Edition)
IS - 4
ER -