Hierarchical shared multi-channel scratch pad memory architecture for embedded MPSoC

To support the real-time and low latency memory accesses of embedded applications, a kind of CMP memory architecture is proposed. The sharable multi-channel scratch pad memory is designed and implemented to be multi-access cross memory. The shared multi-channel scratch pad memory (SPM) space is automatically distributed to concurrent applications according to the size. Both of the above design schemes aim on improving the utilization of the shared SPM space. The experimental results indicate that no matter what to compare with shared Cache architecture or to compare with the state-of-the-art, HSMC-SPM is a kind of low-power and performance-efficient CMP memory architecture.