FPGA implementation of Turbo decoder in frequency-hopping system

Implementation scheme of field programmable gate array (FPGA) Turbo decoder is presented. Max-Log-Map algorithm and modular design methodology are employed and the decoder is able to decode variable length Turbo codes. A Turbo decoder with variable packet length has been implemented in a Xilinx xc3s2000-4fg676 FPGA circuit. Under the condition that packet length is 1024 bit and iteration times is 5, the throughput of the decoder is 1.261 Mbit/s and decoding latency is 0.812 ms. The designed Turbo decoder is tested under additive white Gaussian noise and partial-band noise interference channel for its bit error rate performance. Adaptive gain control (AGC) is employed under partial-band noise interference channel. Simulation results showed that the performance of decoder is improved with AGC.