FPGA design and implementation of high speed multi-rate LDPC encoder based on DVB-S2

An encoder architecture of low density parity check (LDPC) code defined in DVB-S2 standard is proposed. The power dissipation of the computation circuit is reduced obviously through the smart exploitation of the random characteristic of the input data sequence. Furthermore, a design scheme of LDPC encoder with two parallel inputs is presented, which doubles the processing information rate. The multi-rate LDPC encoder with two parallel inputs was implemented on the field programmable gate array (FPGA) XC4VLX25-10SF363, and was tested under the experimental system. The tested results showed that the encoder could work normally with the processing rate up to 328Mbit/s, which could satisfy the requirements of high speed synchronous digital hierarchy (SDH) transmission application. Additionally, this encoder is flexible to implement encoding of LDPC code with similar parity check matrices via reconfiguration.