FPGA-Based Implementation of Reconfigurable Floating-Point FIR Digital Filter

As a critical digital signal processing method, finite impulse response (FIR) digital filter is widely used in radar signal processing, synthetic aperture radar (SAR) signal processing, etc. Furthermore, an efficient FIR hardware implementation contributes to the practical application of these processing. However, as a computation-intensive operation, the multiple high order FIR digital filter consumes a lot of hardware resources when implemented in commonly used chips such as field-programmable gate array (FPGA). In this paper, a reconfigurable FIR digital filter architecture is presented, which can perform different order FIR filtering operation without FPGA re-programming. In the experiment, the proposed FIR digital filter architecture was implemented and validated on the Xilinx Zedboard Evaluation Kit. The experimental results demonstrate that this design has a low consumption of hardware resources and can achieve real-time processing performance for digital signal processing in the practical applications.