@inproceedings{b89cf5d204f443928905c440e2ef49b9,
title = "Efficient and Flexible 2-D Data Controller for SAR Imaging System",
abstract = "Controlling of two-dimensional data is a very critical part in synthetic aperture radar (SAR) imaging systems. This paper presents a field-programmable gate array (FGPA)-based Double-Data-Rate three Synchronous Dynamic Random Access Memory (DDR3 SDRAM) data controller which can efficiently access arbitrary length data points along any one-dimensional direction from any position in two-dimensional data. To improve the efficiency of transposition, the address of data in DDR3 is obtained by sub-matrix cross-mapping method. A complete SAR imaging system with the proposed controller is implemented and validated in a XC7VX690T FPGA platform as the experiment. Our experimental results demonstrate that this design can improve system parallelism by reducing the use of RAM resources. And 5.83s is required to get the complete imaging result with the SAR raw data of 16384 \times 16384.",
keywords = "DDR3 SDRAM, FPGA, Matrix transpose method, Synthetic aperture radar (SAR)",
author = "Tianyun Sun and Yizhuang Xie and Bingyi Li and He Chen and Xiaoning Liu and Liang Chen",
note = "Publisher Copyright: {\textcopyright} 2018 IEEE.; 2018 IEEE High Performance Extreme Computing Conference, HPEC 2018 ; Conference date: 25-09-2018 Through 27-09-2018",
year = "2018",
month = nov,
day = "26",
doi = "10.1109/HPEC.2018.8547533",
language = "English",
series = "2018 IEEE High Performance Extreme Computing Conference, HPEC 2018",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "2018 IEEE High Performance Extreme Computing Conference, HPEC 2018",
address = "United States",
}