Digital random sequence generation algorithm and VLSI implementation

A VLSI array synthesizing digital random sequence algorithm is proposed, and its Application-specific integrated circuit (ASIC) design of the General random number generator (GRNG) which can generate digital random sequence with uniform distribution, exponential distribution, Rayleigh distribution and Gaussian distribution is introduced. In this algorithm, the Box-Muller equation is adopted for real-time generating random number using hardware, and one improved Tausworthe sequence generating principle is proposed to speed up the generation and improve the signal quality. Moreover, the pipelined Coordinate rotation digital computer (CORDIC) mapping algorithm is used to increases the throughput. The proposed GRNG is implemented with SMIC one-poly six-metal 0.18μm CMOS technology. The ASIC core occupies 1.8 × 1.8mm² die area which generates 16-bit or 32-bit samples up to 4σ, the peak throughput of the ASIC is 420 million samples per second, and the peak power dissipation, which includes the power of I/O, is 416mW in active mode, and 106mW in standby mode respectively in typical operation condition.