Digital circuit design of a specific target simulator

Zhe Zheng; Yan Jun Wang; Jia Qi Li; Si Liang Wu

Digital circuit design of a specific target simulator

Zhe Zheng^*, Yan Jun Wang, Jia Qi Li, Si Liang Wu

^*此作品的通讯作者

信息与电子学院

Beijing Institute of Technology

科研成果: 期刊稿件 › 文章 › 同行评审

摘要

The basic structure and working principle of a radar dynamic signal simulator are introduced. With Virtex-II series FPGA as the core, and based on USB controller and mass-memory, the simulator utilizes fully the optimization technology suitable the FPGA's structure and realizes the dynamic signal simulator's digital video signal processing. At the same time, the output waveform is given.

源语言	英语
页（从-至）	1950-1953
页数	4
期刊	Xi Tong Gong Cheng Yu Dian Zi Ji Shu/Systems Engineering and Electronics
卷	26
期	12
出版状态	已出版 - 12月 2004

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@article{d3901f960da048c8b992315ba5a9316a,

title = "Digital circuit design of a specific target simulator",

abstract = "The basic structure and working principle of a radar dynamic signal simulator are introduced. With Virtex-II series FPGA as the core, and based on USB controller and mass-memory, the simulator utilizes fully the optimization technology suitable the FPGA's structure and realizes the dynamic signal simulator's digital video signal processing. At the same time, the output waveform is given.",

keywords = "Controller, Design, Digital circuit, Target simulator",

author = "Zhe Zheng and Wang, {Yan Jun} and Li, {Jia Qi} and Wu, {Si Liang}",

year = "2004",

month = dec,

language = "English",

volume = "26",

pages = "1950--1953",

journal = "Xi Tong Gong Cheng Yu Dian Zi Ji Shu/Systems Engineering and Electronics",

issn = "1001-506X",

publisher = "Chinese Institute of Electronics",

number = "12",

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TY - JOUR

T1 - Digital circuit design of a specific target simulator

AU - Zheng, Zhe

AU - Wang, Yan Jun

AU - Li, Jia Qi

AU - Wu, Si Liang

PY - 2004/12

Y1 - 2004/12

N2 - The basic structure and working principle of a radar dynamic signal simulator are introduced. With Virtex-II series FPGA as the core, and based on USB controller and mass-memory, the simulator utilizes fully the optimization technology suitable the FPGA's structure and realizes the dynamic signal simulator's digital video signal processing. At the same time, the output waveform is given.

AB - The basic structure and working principle of a radar dynamic signal simulator are introduced. With Virtex-II series FPGA as the core, and based on USB controller and mass-memory, the simulator utilizes fully the optimization technology suitable the FPGA's structure and realizes the dynamic signal simulator's digital video signal processing. At the same time, the output waveform is given.

KW - Controller

KW - Design

KW - Digital circuit

KW - Target simulator

UR - http://www.scopus.com/inward/record.url?scp=12844253353&partnerID=8YFLogxK

M3 - Article

AN - SCOPUS:12844253353

SN - 1001-506X

VL - 26

SP - 1950

EP - 1953

JO - Xi Tong Gong Cheng Yu Dian Zi Ji Shu/Systems Engineering and Electronics

JF - Xi Tong Gong Cheng Yu Dian Zi Ji Shu/Systems Engineering and Electronics

IS - 12

ER -

Digital circuit design of a specific target simulator

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