Design and Optimization of High Speed PLL Based on 90 nm CMOS Process

A high speed phase locked loop (PLL) was designed based on TSMC 90 nm CMOS process. In order to optimize phase noise and reference spur, the main modules of PLL such as charge pump and LC voltage controlled oscillator (VCO) were analyzed and improved. The design method of multi-modulus divider (MMD) was studied in detail. The layout of the high speed PLL was optimized and whole chip area was arranged in 490 μm×990 μm. The testing results show that, the in-band phase noise can reach -90 dBc at 1 MHz frequency offset and the reference spur is -56.797 dBc.