Design and implementation of multi-rate wideband demodulator

Algorithms of timing recovery loop and carrier recovery loop employed are analyzed and simulated. Based on this, the architecture and hardware implementation schemes of synchronizers of the wideband multi-rate demodulator are proposed. According to the characteristics of QPSK signal, the algorithm of carrier synchronization is simplified. Performance of the implemented demodulator is tested and analyzed. The test results showed that the demodulator can work normally at symbol rates from 2 MS/s to 45 MS/s. When the symbol rate is below 10 MS/s, the IF loop BER performance is less than 1 dB away from the theoretical limit. When the symbol rate is above 10 MS/s, the IF loop BER performance is less than 1.6 dB away from the theoretical limit.