DESIGN AND IMPLEMENTATION OF A CONFIGURABLE PARALLEL FFT PROCESSOR IN ONBOARD SAR IMAGING SYSTEM BASED ON FPGA

Spaceborne Synthetic Aperture Radar (SAR) plays an important role in the field of emergency disaster reduction. In order to meet the stringent timeliness requirements in onboard SAR data processing, this paper proposes a configurable four-channel parallel FFT processor, which serves as the core of SAR imaging processing. This processor is capable of supporting up to 128K-point FFT operations. Additionally, it supports radix-2 time decimation FFT concatenation processing, radix-4 time decimation FFT concatenation processing, radix-2 frequency decimation FFT concatenation processing, and radix-4 frequency decimation FFT concatenation processing, all of which can be flexibly configured based on data structure. This processor is implemented on the Xilinx Virtex-7 XC7VX690T FPGA and can achieve a maximum FFT processing capability of 128K points at a frequency of 300MHz. The evaluation and analysis results demonstrate that the processor reaches a higher processing rate, effectively meeting the demanding requirements for efficient spaceborne processing.