Crosstalk on sampling clock and additive dither in radio receiver if digitization

Radio receiver intermediate frequency digitization generally requires high resolution of analog-to-digital conversion with wide bandwidth. The sampling clock performance is a key concern and is widely investigated in the published literatures. However, most of the issues mainly focused on the clock jitter with white Gaussian noise only. This paper present a more realistic analog-to-digital conversion analysis model based on the actual circuit noise conditions, particularly investigating on the clock jitter error with the combination of Gauss distribution noise and circuit noise (interference). An analytical expression for the A/D conversion with the combined clock jitter error is developed. The computer simulations are presented, which showed excellent agreement with the developed expression. Also, a solution of additive dithering technique is present to reduce the effect of circuit crosstalk on sampling clock.