ASIC design for real-time reconfigurable FFT processor

A complex data fast Fourier transforms (FFT) processor is proposed. This FFT processor can be reconfigured as a 4, 16, 64, 256 or 1024 points computation. Radix-4 pipelined architecture is adopted for 16 and 64 points computation. Two-dimensional architecture is adopted for 256 and 1024 points computation. Block-floating point algorithm is adopt. The ASIC design is synthesized, placed and routed using Synopsys with SMIC CMOS 0.18 μm library. When the processor operates continuously at 100 MHz, it can calculate the first 1024 complex points FFT in 24.8 μs, and then get 1024 results in each 10.24 μs. The chip has been used in a kind of wide band digital receiver.