Analysis on signal crosstalk effects on sampling clock and analog-to-digital system

An analog-to-digital system performance analysis model is presented based on the real circuit system. The circuit signal crosstalk on sampling clock and its effect on analog-to-digital system performance are studied based on the model. An analytical expression for the A/D conversion with such combined clock jitter error is developed. The expression shows that the combined clock error can generate infinite harmonic components on the converted digital signal. Computer simulations are in agreement with the developed expression. Also, a real experiment shows the evidence of the circuit noise influence on A/D performance and brings forth a comprehensive evaluation of analog-to-digital system design. This paper offers A/D designers a thumb rule to reduce the discrepancy between the actual circuit performance and the official figure imprinted on data sheet.