An efficient vlsi architecture and implementation of motion compensation for video decoder

Chao Cao*, Li Zhen Yu, Yanjun Zhang

*此作品的通讯作者

科研成果: 书/报告/会议事项章节会议稿件同行评审

摘要

Motion compensation calculation of video decoder frequently access the video data which are stored in external memory, thus efficient memory access is critical in the design of decoder. An advanced parallel multi-pipe line architecture of Motion compensation is proposed in this paper, which fulfilled different of picture prediction modes employed by multi standard video decoder. In this architecture, buffering mechanism for the reference data is used to reduce external memory access, and DMA is used to control data transformation between modules. Compared with traditional memory fetch module, the proposed architecture reduces 30%~40% video decoding cycle in H.264 decoding. Synthetically result shows that timing and the area of this design are both satisfied the requirement of video decoder.

源语言英语
主期刊名Communications and Information Processing - International Conference, ICCIP 2012, Revised Selected Papers
556-563
页数8
版本PART 2
DOI
出版状态已出版 - 2012
活动2012 International Conference on Communications and Information Processing, ICCIP 2012 - Aveiro, 葡萄牙
期限: 7 3月 201211 3月 2012

出版系列

姓名Communications in Computer and Information Science
编号PART 2
289 CCIS
ISSN(印刷版)1865-0929

会议

会议2012 International Conference on Communications and Information Processing, ICCIP 2012
国家/地区葡萄牙
Aveiro
时期7/03/1211/03/12

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