An 85-95.2 GHz transformer-based injection-locked frequency tripler in 65nm CMOS

A W-band transformer-based injection-locked frequency tripler (T-ILFT) is designed and implemented in 65nm standard CMOS technology using a O.8V supply voltage. The use of injection locking topology with on-chip transformer provides several advantages over conventional design. Occupying an chip area of O.089mm2 (including buffers), the T-ILFT achieves an input sensitivity of -15dBm and a continuous locking range from 85 to 95.2GHz with 4dBm input power. T he measured phase noise degradation from that of the input signal source is only 9.8dB at IMHz offset. T he harmonic suppressions for the first and second harmonics are measured to be 32.9dB and 38.5dB, respectively. T he power consumption is only 5.2mW for T-ILFT and 14.6mW for output buffers. To the authors' best knowledge, this T-ILFT achieves the highest operation frequency for injection-locked-based frequency multipliers, reported to date.