TY - GEN
T1 - A novel three-phase software phase-locked loop based on frequency-locked loop and initial phase angle detection phase-locked loop
AU - Wang, Liang
AU - Jiang, Qirong
AU - Hong, Lucheng
PY - 2012
Y1 - 2012
N2 - This paper proposes a new three-phase software phase-locked loop (SPLL) which operates fast and accurately in unbalanced, polluted and frequency deviated circumstances. This new proposed SPLL consists of frequency-locked loop (FLL) and initial phase angle detection PLL. The FLL employs differential algorithm to detect frequency error which could immune to phase jumps and voltage sharp changes. A frequency adaptive digital filter (FADF) is included in FLL to reject harmonics. The FADF uses two strategies to sweep away disturbing signals in a synchronous reference domain. Firstly, specific order harmonics are eliminated by multistage application of delayed signal cancellation (DSC) using estimated delayed signals. Excellent steady-state performance of multistage DSC to reject harmonics is achieved with the help of FLL and interpolation strategy. Secondly, a conventional low-pass (LP) filter damps the rest higher frequency harmonics and noises. Initial phase angle detection PLL could have a high cutoff frequency due to good performance of FADF. Simulations prove the new SPLL responds fast and has precise steady-state output.
AB - This paper proposes a new three-phase software phase-locked loop (SPLL) which operates fast and accurately in unbalanced, polluted and frequency deviated circumstances. This new proposed SPLL consists of frequency-locked loop (FLL) and initial phase angle detection PLL. The FLL employs differential algorithm to detect frequency error which could immune to phase jumps and voltage sharp changes. A frequency adaptive digital filter (FADF) is included in FLL to reject harmonics. The FADF uses two strategies to sweep away disturbing signals in a synchronous reference domain. Firstly, specific order harmonics are eliminated by multistage application of delayed signal cancellation (DSC) using estimated delayed signals. Excellent steady-state performance of multistage DSC to reject harmonics is achieved with the help of FLL and interpolation strategy. Secondly, a conventional low-pass (LP) filter damps the rest higher frequency harmonics and noises. Initial phase angle detection PLL could have a high cutoff frequency due to good performance of FADF. Simulations prove the new SPLL responds fast and has precise steady-state output.
KW - Delayed Signal Cancellation
KW - Digital Filter
KW - Frequency-Locked Loop
KW - Grid Synchronization
KW - Software Phase-Locked Loop
UR - http://www.scopus.com/inward/record.url?scp=84872964523&partnerID=8YFLogxK
U2 - 10.1109/IECON.2012.6388816
DO - 10.1109/IECON.2012.6388816
M3 - Conference contribution
AN - SCOPUS:84872964523
SN - 9781467324212
T3 - IECON Proceedings (Industrial Electronics Conference)
SP - 150
EP - 155
BT - Proceedings, IECON 2012 - 38th Annual Conference on IEEE Industrial Electronics Society
T2 - 38th Annual Conference on IEEE Industrial Electronics Society, IECON 2012
Y2 - 25 October 2012 through 28 October 2012
ER -