A novel low-overhead fault tolerant parallel-pipelined FFT design

Yu Xie; Chen Yang; Chuang An Mao; He Chen; Yi Zhuang Xie

doi:10.1109/DFT.2017.8244461

A novel low-overhead fault tolerant parallel-pipelined FFT design

Yu Xie, Chen Yang, Chuang An Mao, He Chen^*, Yi Zhuang Xie

^*此作品的通讯作者

信息与电子学院

Beijing Institute of Technology

科研成果: 书/报告/会议事项章节 › 会议稿件 › 同行评审

8 引用（Scopus）

摘要

As soft errors become a significant threat to modern electronic systems, the first priority of protection against soft errors should be decreasing resource consumption. This brief proposes a novel low-overhead fault tolerant FFT design, combining modified reduced precision redundancy (RPR) method and error correction codes (ECCs). RPR can lower the hardware overhead when compared with traditional full-precision redundancy techniques, especially when resource of the original design is huge. ECCs are cost-efficient for achieving fault tolerance on our parallel-pipelined FFT. As an example, an FPGA implementation of a four-channel 16K-point FFT is presented, which demonstrates that the proposed scheme can further reduce the overhead of fault tolerance designs.

源语言	英语
主期刊名	2017 IEEE Int. Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2017
出版商	Institute of Electrical and Electronics Engineers Inc.
页	1-4
页数	4
ISBN（电子版）	9781538603628
DOI	https://doi.org/10.1109/DFT.2017.8244461
出版状态	已出版 - 28 6月 2017
活动	13th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2017 - Cambridge, 英国期限: 23 10月 2017 → 25 10月 2017

出版系列

姓名	2017 IEEE Int. Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2017
卷	2018-January

会议

会议	13th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2017
国家/地区	英国
市	Cambridge
时期	23/10/17 → 25/10/17

访问文件

10.1109/DFT.2017.8244461

其它文件与链接

链接到 Scopus 的出版物

引用此

Xie, Y., Yang, C., Mao, C. A., Chen, H., & Xie, Y. Z. (2017). A novel low-overhead fault tolerant parallel-pipelined FFT design. 在 2017 IEEE Int. Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2017 (页码 1-4). (2017 IEEE Int. Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2017; 卷 2018-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/DFT.2017.8244461

Xie, Yu ; Yang, Chen ; Mao, Chuang An 等. / A novel low-overhead fault tolerant parallel-pipelined FFT design. 2017 IEEE Int. Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2017. Institute of Electrical and Electronics Engineers Inc., 2017. 页码 1-4 (2017 IEEE Int. Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2017).

@inproceedings{76107cd8e56545e1a32d3a8e44b46ecb,

title = "A novel low-overhead fault tolerant parallel-pipelined FFT design",

abstract = "As soft errors become a significant threat to modern electronic systems, the first priority of protection against soft errors should be decreasing resource consumption. This brief proposes a novel low-overhead fault tolerant FFT design, combining modified reduced precision redundancy (RPR) method and error correction codes (ECCs). RPR can lower the hardware overhead when compared with traditional full-precision redundancy techniques, especially when resource of the original design is huge. ECCs are cost-efficient for achieving fault tolerance on our parallel-pipelined FFT. As an example, an FPGA implementation of a four-channel 16K-point FFT is presented, which demonstrates that the proposed scheme can further reduce the overhead of fault tolerance designs.",

keywords = "ECCs, FFT, FPGA, RPR, fault tolerant",

author = "Yu Xie and Chen Yang and Mao, {Chuang An} and He Chen and Xie, {Yi Zhuang}",

note = "Publisher Copyright: {\textcopyright} 2017 IEEE.; 13th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2017 ; Conference date: 23-10-2017 Through 25-10-2017",

year = "2017",

month = jun,

day = "28",

doi = "10.1109/DFT.2017.8244461",

language = "English",

series = "2017 IEEE Int. Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2017",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "1--4",

booktitle = "2017 IEEE Int. Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2017",

address = "United States",

}

Xie, Y, Yang, C, Mao, CA, Chen, H & Xie, YZ 2017, A novel low-overhead fault tolerant parallel-pipelined FFT design. 在 2017 IEEE Int. Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2017. 2017 IEEE Int. Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2017, 卷 2018-January, Institute of Electrical and Electronics Engineers Inc., 页码 1-4, 13th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2017, Cambridge, 英国, 23/10/17. https://doi.org/10.1109/DFT.2017.8244461

A novel low-overhead fault tolerant parallel-pipelined FFT design. / Xie, Yu; Yang, Chen; Mao, Chuang An 等.
2017 IEEE Int. Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2017. Institute of Electrical and Electronics Engineers Inc., 2017. 页码 1-4 (2017 IEEE Int. Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2017; 卷 2018-January).

科研成果: 书/报告/会议事项章节 › 会议稿件 › 同行评审

TY - GEN

T1 - A novel low-overhead fault tolerant parallel-pipelined FFT design

AU - Xie, Yu

AU - Yang, Chen

AU - Mao, Chuang An

AU - Chen, He

AU - Xie, Yi Zhuang

PY - 2017/6/28

Y1 - 2017/6/28

N2 - As soft errors become a significant threat to modern electronic systems, the first priority of protection against soft errors should be decreasing resource consumption. This brief proposes a novel low-overhead fault tolerant FFT design, combining modified reduced precision redundancy (RPR) method and error correction codes (ECCs). RPR can lower the hardware overhead when compared with traditional full-precision redundancy techniques, especially when resource of the original design is huge. ECCs are cost-efficient for achieving fault tolerance on our parallel-pipelined FFT. As an example, an FPGA implementation of a four-channel 16K-point FFT is presented, which demonstrates that the proposed scheme can further reduce the overhead of fault tolerance designs.

AB - As soft errors become a significant threat to modern electronic systems, the first priority of protection against soft errors should be decreasing resource consumption. This brief proposes a novel low-overhead fault tolerant FFT design, combining modified reduced precision redundancy (RPR) method and error correction codes (ECCs). RPR can lower the hardware overhead when compared with traditional full-precision redundancy techniques, especially when resource of the original design is huge. ECCs are cost-efficient for achieving fault tolerance on our parallel-pipelined FFT. As an example, an FPGA implementation of a four-channel 16K-point FFT is presented, which demonstrates that the proposed scheme can further reduce the overhead of fault tolerance designs.

KW - ECCs

KW - FFT

KW - FPGA

KW - RPR

KW - fault tolerant

UR - http://www.scopus.com/inward/record.url?scp=85046028005&partnerID=8YFLogxK

U2 - 10.1109/DFT.2017.8244461

DO - 10.1109/DFT.2017.8244461

M3 - Conference contribution

AN - SCOPUS:85046028005

T3 - 2017 IEEE Int. Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2017

SP - 1

EP - 4

BT - 2017 IEEE Int. Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2017

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 13th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2017

Y2 - 23 October 2017 through 25 October 2017

ER -

Xie Y, Yang C, Mao CA, Chen H, Xie YZ. A novel low-overhead fault tolerant parallel-pipelined FFT design. 在 2017 IEEE Int. Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2017. Institute of Electrical and Electronics Engineers Inc. 2017. 页码 1-4. (2017 IEEE Int. Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2017). doi: 10.1109/DFT.2017.8244461

A novel low-overhead fault tolerant parallel-pipelined FFT design

摘要

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