TY - JOUR
T1 - A new hardware architecture of high-performance real-time texture classification system based on FPGA
AU - Zhang, Yanjun
AU - Guo, Xin
AU - Guo, Hongchen
AU - Zhang, Yichen
N1 - Publisher Copyright:
© The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature 2024.
PY - 2025/1
Y1 - 2025/1
N2 - The visual system is essential as a critical source for intelligent robots to acquire external information. Nevertheless, the real-time performance of existing approaches remains inadequate. To address this, a new high-performance target classification system based on FPGA has been developed as part of the visual system. This system optimizes the hardware architecture of the target classification algorithm, incorporating a novel method aimed at boosting parallelism to improve real-time performance. The system is implemented on the Xilinx Zynq-7045 FPGA. Experimental results demonstrate that, for a grayscale image with a resolution of 128 × 128, the feature extraction time is merely 85.64 µs, achieving a speed three orders of magnitude greater than that of the MATLAB platform. Additionally, the resource consumption of this design is lower than that of existing hardware architectures.
AB - The visual system is essential as a critical source for intelligent robots to acquire external information. Nevertheless, the real-time performance of existing approaches remains inadequate. To address this, a new high-performance target classification system based on FPGA has been developed as part of the visual system. This system optimizes the hardware architecture of the target classification algorithm, incorporating a novel method aimed at boosting parallelism to improve real-time performance. The system is implemented on the Xilinx Zynq-7045 FPGA. Experimental results demonstrate that, for a grayscale image with a resolution of 128 × 128, the feature extraction time is merely 85.64 µs, achieving a speed three orders of magnitude greater than that of the MATLAB platform. Additionally, the resource consumption of this design is lower than that of existing hardware architectures.
KW - FPGA
KW - Incremental SVM
KW - Median robust extended local binary pattern
KW - Real-time texture classification system
UR - http://www.scopus.com/inward/record.url?scp=85213573768&partnerID=8YFLogxK
U2 - 10.1007/s11227-024-06705-6
DO - 10.1007/s11227-024-06705-6
M3 - Article
AN - SCOPUS:85213573768
SN - 0920-8542
VL - 81
JO - Journal of Supercomputing
JF - Journal of Supercomputing
IS - 1
M1 - 344
ER -